1. Field of the Invention
This invention relates generally to memory devices and, more particularly, to an apparatus and method for storing analog or multi-level signals in a memory device.
2. Description of the Related Art
Electronic storage devices are currently capable of storing analog signals. In general, these storage devices use one of two approaches to store analog signals. One approach is to convert the analog signal into a digital signal using an analog-to-digital ("A/D") convertor. The digital signal is then stored in a conventional digital memory device, such as, for example, SRAM and DRAM memories. While the digital approach provides high quality and accurate reproduction of the analog signal, such as an audio signal, the use of A/D and D/A convertors increases the overall complexity of the memory device. Additionally, digital storage of analog signals typically requires a large memory capacity.
The other approach involves storing the analog signal directly to a nonvolatile memory cell. FIG. 1 represents a conventional analog storage device 100. Conventional analog storage device 100 includes a sample and hold ("S/H") circuit 102, a comparator 104, a comparator send circuit 106, a comparator entry circuit 108, a high voltage charger and sensor 110, and a memory cell 112. Typically, memory cell 112 is part of a large array of memory cells; however, for simplicity the example is limited to one memory cell 112.
FIG. 2 represents a flow chart 200 illustrating how analog storage device 100 operates. First, S/H circuit 102 samples an analog signal at a predetermined sample rate to obtain and hold a sample voltage (step 202), which is indicative of the analog signal. Next, S/H circuit 102 sends the sample voltage to a first input of comparator 104 (step 204). Comparator 104 compares the sample voltage at the first input of comparator 104 to the voltage at a second input of comparator 104 (step 206). During the first iteration of this procedure, the second input of comparator 104 is initialized to a predetermined value. Based on the comparison, comparator 104 determines whether the first input and the second input are approximately equal (step 208). If comparator 104 determines the inputs are approximately equal (i.e., within a predetermined tolerance), then the voltage level currently stored in memory cell 112 is considered equal to the sample voltage and the process stops (step 210), otherwise comparator send circuit 106 sends a charge signal to high voltage charger 110 (step 212). High voltage charger 110 increases the voltage stored in memory cell 112 by sending a programming voltage pulse to memory cell 112 for a predetermined length of time (step 214). After a predetermined length of time, high voltage charger 110 increases the magnitude of the programming voltage pulse by a predetermined amount (step 216). Comparator entry circuit 108 then senses the voltage signal currently stored in memory cell 112 (step 218). Comparator entry circuit 108 sends the sensed voltage read from memory cell 112 to the second input of comparator 104 (step 220). Steps 206 to 220 are repeated until the sampled voltage and the voltage sensed from memory cell 112 are equal, at which time the process stops at step 210. U.S. Pat. No. 4,890,259, issued to Richard T. Simko, discloses details of such a conventional analog storage device.
Thus, the second approach to storing analog signals uses an iterative, trail and error programming process. In other words, the memory cell receives an initial programming voltage pulse corresponding to a low sample voltage. The programming voltage pulse is then incremented by a fraction of a volt. This process of programming and incrementing continues until the voltage programmed into the memory cell equals the sampled analog input voltage. In the above noted U.S. Pat. No. 4,890,259, charging the memory in this fashion can involve up to 400 iterations. Programming the memory cell through the above described iterated process, therefore, takes a significant amount of programming time. It would be desirable to reduce the programming time.